Transistor structure with reduced parasitic &#34;side wall&#34; characteristics

ABSTRACT

A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).

RELATED APPLICATION(S)

This application is a divisional of U.S. patent application Ser. No.14/585,211, filed on Dec. 30, 2014, entitled “TRANSISTOR STRUCTURE WITHREDUCED PARASITIC SIDE WALL CHARACTERISTICS”, the contents of which areincorporated herein by reference.

TECHNICAL FIELD

Various embodiments relate to a transistor structure with a reducedparasitic “side wall” transistor regions.

BACKGROUND

Certain low power analog circuits utilize various types of field effecttransistors (e.g. complementary metal-oxide-semiconductor “CMOS”;metal-oxide-semiconductor field-effect transistor “MOSFET”;metal-insulation-semiconductor field-effect transistor “MISFET”; etc.).Some low power applications use matched pairs of such transistors,however the “matching” properties of these transistors begins to changefor the worse at lower operating currents. This is because, in low powerapplications, the transistors operate in the so-called “Weak Inversion”mode (or sub-threshold region), in which a low drain current (I_(ds)) isflowing. Further, when operating in the sub-threshold region, variousphenomena which adversely affect the performance of the transistor maybecome dominant. Some of these adverse phenomena are related to themechanical structure of a typical field effect transistor. In mostMOSFET devices, so-called “side wall” transistors form at the edges ofthe gate region and adversely affect the performance of such devices,particularly when a closely matched pair of transistors is required fora given application.

SUMMARY

In various embodiments, a transistor structure is provided. Thetransistor structure may include a well region of a first impurity typein a substrate with at least one transistor in the well region, astructure of the first impurity type enclosing the well region, and atrench or a field oxide isolation layer enclosing the structure.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, like reference characters generally refer to the sameparts of the disclosure throughout the different views. The drawings arenot necessarily to scale, emphasis instead generally being placed uponillustrating the principles of the disclosure. In the followingdescription, various embodiments of the disclosure are described withreference to the following drawings, in which:

FIG. 1 shows, in accordance with a potential embodiment, a longitudinalcross-sectional representation of a transistor structure;

FIG. 2 shows, according to an embodiment, a transverse cross-sectionalrepresentation of a transistor structure;

FIG. 3 shows a planar top-down view of an embodiment of the transistorstructure of FIGS. 1 & 2;

FIG. 4 shows, according to an embodiment a planar top-down view of aquad-transistor structure;

FIG. 5 shows, according to an embodiment a planar top-down view of amulti-transistor structure including eight transistors;

FIG. 6 shows, according to an embodiment a planar top-down view of aring-shaped transistor structure.

DESCRIPTION

The following detailed description refers to the accompanying drawingsthat show, by way of illustration, specific details and embodiments inwhich the disclosure may be practiced.

The word “exemplary” is used herein to mean “serving as an example,instance, or illustration”. Any embodiment or design described herein as“exemplary” is not necessarily to be construed as preferred oradvantageous over other embodiments or designs.

The word “over” used with regards to a deposited material formed “over”a side or surface may be used herein to mean that the deposited materialmay be formed “directly on”, e.g. in direct contact with the impliedside or surface. The word “over” used with regards to a depositedmaterial formed “over” a side or surface may be used herein to mean thatthe deposited material may be formed “indirectly on” the implied side orsurface with one or more additional layers being arranged between theimplied side or surface and the deposited material.

In various embodiments, a transistor with reduced parasitic “side wall”transistor regions is disclosed.

The transistor structure 100, as illustrated in FIGS. 1-3, may include asubstrate 102, a well region 101 of a first impurity type in thesubstrate 102, at least one transistor 104 formed at least partially onthe well region 101, a portion of the well region 101 may be implementedas a transistor channel 108 of the transistor 104. The transistor 104may include a first diffusion region 104 a of a second impurity type inthe well region 101, and a second diffusion region 104 b of the secondimpurity type in the well region 101. According to an embodiment, thetransistor structure 100 may include a structure of the first impuritytype 110 in the substrate 102 enclosing the well region 101. Accordingto various embodiments, the structure of the first impurity type 110 isimplemented as a bulk diffusion region for connection to the well region101. The transistor structure 100 may further include a trench or fieldoxide isolation layer 112 in the substrate 102 enclosing the structureof the first impurity type 110. In some embodiments, an impurityconcentration in the structure of the first impurity type 110 is higherthan an impurity concentration in the well region 101.

In various embodiments, the transistor 104 may further include an oxidelayer 114 disposed over the channel 108, a gate electrode 116 on theoxide layer 114, a source electrode 118 on the first diffusion region104 a, a drain electrode 120 on the second diffusion region 104 b, andat least one body connection electrode 122 on the structure of the firstimpurity type 110. According to various embodiments, the transistor 104may include at least one lightly doped source region 124 of the secondimpurity type extending from the perimeter of the first diffusion region104 a and into the channel 108, and at least one lightly doped drainregion 126 of the second impurity type extending from the perimeter ofthe second diffusion region 104 b and into the channel 108.

According to various embodiments, the substrate 102 may include oressentially consist of various materials, e.g. a semiconductor materialsuch as various elemental and/or compound semiconductors. The substrate102 may include or essentially consist of, for example, glass, and/orvarious polymers. The substrate 102 may be a silicon-on-insulator (SOI)structure. In various embodiments, the substrate 102 may include oressentially consist of one or more of the following materials: apolyester film, a thermoset plastic, a metal, a metalized plastic, ametal foil, and a polymer. In some embodiments, the substrate 102 may bea multilayer substrate. According to various embodiments, the substrate102 may have a thickness T1 in the range from about 10 μm to about 700μm. According to various embodiments, the substrate 102 may have athickness T1 which may be any thickness desirable for a givenapplication. According to various embodiments, the substrate 102 may beformed into any shape that may be desired for a given application.

In various embodiments, the well region 101 may be formed in and/or onthe substrate 102. The well region 101 may be an impurity doped regionin the substrate 102, e.g. an n-type or p-type region in a semiconductorsubstrate. In some embodiments, the well region 101 may be formed in thesubstrate 102 through various techniques, e.g. vapor-phase epitaxy,diffusion, and/or ion implantation, etc. In various embodiments, thewell region 101 may have an impurity concentration in the range fromabout 10¹³ cm⁻³ to about 10¹⁸ cm⁻³. According to various embodiments,the well region may have a thickness T2, in the range from about 0.5 μmto about 10 μm. According to a first example of an embodiment, the wellregion 101 is implemented as a p-type well region in a semiconductorsubstrate 102. In a second example of an embodiment, the well region 101is implemented as an n-type well region in a semiconductor substrate102.

According to various embodiments, the transistor structure 100 mayinclude a first diffusion region 104 a. In various embodiments, thefirst diffusion region 104 a may be formed in and/or on the well region101. In some embodiments, the first diffusion region 104 a isimplemented as an impurity doped region in the well region 101, e.g. ann-type or p-type region in a semiconductor substrate. In someembodiments, the first diffusion region 104 a is formed in the wellregion 101 through various techniques, e.g. vapor-phase epitaxy,diffusion, and/or ion implantation, etc. According to variousembodiments, the first diffusion region 104 a may have an impurityconcentration in the range from about 10¹⁸ cm⁻³ to 5×10²¹ cm⁻³.According to an embodiment, the first diffusion region 104 a isimplemented as a p-type region in the well region 101. In anotherembodiment, the first diffusion region 104 a is implemented as an n-typewell region in the well region 101. According to various embodiments,the first diffusion region 104 a may serve as a source and/or drainregion for the transistor 104. In at least one embodiment and variousother embodiments, the first diffusion region 104 a is implemented as ann++ type doped source region for the transistor 104. In some embodimentsand various other embodiments, the first diffusion region 104 a isimplemented as a p++ type doped source or drain region 104 a for thetransistor 104. In at least one embodiment, the second diffusion region104 a may be implemented as a common source or drain region for aplurality of transistors.

According to various embodiments, the transistor structure 100 mayinclude a second diffusion region 104 b, which may be substantiallysimilar to the first diffusion region 104 a, described above and maycontain many of the same materials.

In various embodiments, the transistor channel 108 may be formed betweenthe first diffusion region 104 a and the second diffusion region 104 b.The transistor channel 108 may have a length, shown in FIGS. 1 & 3 andindicated by reference character L, which is the distance between thefirst diffusion region 104 a and the second diffusion region 104 b, inthe range from about 0.04 μm to about 10 μm. According to variousembodiments, the length L of the transistor channel 108 may be scaled toany distance desirable for a given application. In various embodimentsthe transistor channel 108 may have a width, indicated by referencecharacter W shown in FIGS. 2 & 3, in the range from about 0.04 μm toabout 10 μm. According to various embodiments, the width W of thetransistor channel 108 may be scaled to any distance desirable for agiven application.

According to various embodiments, the structure of the first impuritytype 110 enclosing the well region 101 may be formed in the substrate102 through various techniques, e.g. vapor-phase epitaxy, diffusion,and/or ion implantation, etc. The structure of the first impurity type110 may have a depth, indicated by reference character D, below thesurface of the substrate 102. In various embodiments the depth D is inthe range from about 1 nm to about 500 nm. The depth D may beimplemented as any depth desirable for a given application. According tovarious embodiments, the structure of the first impurity type 110 mayhave an impurity concentration in the range from about 10¹⁸ cm⁻³ to5×10²¹ cm⁻³. According to various embodiments, the structure of thefirst impurity type 110 may have any impurity concentration desirablefor a given application. According to at least one and various otherembodiments, the structure of the first impurity type 110 is implementedas a p-type or n-type region in the substrate 102 which substantiallyand/or completely encloses the well region 101. According to variousembodiments, the structure of the first impurity type 110 may be formedinto any shape that may be desired for a given application.

According to various embodiments, the transistor structure 100 includesa trench or field oxide isolation layer 112 in the substrate 102enclosing the structure of the first impurity type 110. In anembodiment, the trench or field oxide isolation layer completelyencloses and/or surrounds the structure of the first impurity type 110and serves to electrically isolate and/or insulate the transistorstructure 100 from other electrical components which may be formed onthe substrate 102. According to various embodiments, the trench or fieldoxide isolation layer 112 may be implemented as a so-called shallowtrench isolation (STI) layer. In various embodiments, the trench orfield oxide isolation layer 112 may be implemented as a LOCOS (localoxidation of silicon) field oxide. The trench or field oxide isolationlayer 112 may be composed primarily of and/or may contain variousdielectric materials, e.g. a semiconductor oxide, various high-kdielectrics, etc. According to an embodiment, the trench or field oxideisolation layer 112 may be essentially consist of and/or may contain anyelement desirable for a given application.

According to various embodiments, the transistor structure 100 includesan oxide layer 114, e.g. a gate oxide, over the channel 108. The oxidelayer 114 may have a thickness between about 1 nm and about 50 nm.According to various embodiments, the oxide layer may have any thicknessthat may be desirable for a given application. The oxide layer 114 maybe implemented as a semiconductor oxide layer. In at least oneembodiment, the oxide layer 114 is implemented as a silicon dioxidelayer. In various embodiments, the oxide layer 114 may include and/or becomposed essentially of high-k dielectrics, e.g. various IVb metalsilicates such as hafnium silicates and/or a zirconium silicate.According to an embodiment, the oxide layer may be essentially consistof and/or may contain any element desirable for a given application.According to an embodiment, the oxide layer 114 is implemented as a gateoxide layer situated between the transistor 104 and the channel 108. Theoxide layer, in some embodiments, serves to electrically isolate and/orinsulate at least a portion of the transistor 104 from the channel 108.In some embodiments, the oxide layer 114 does not extend past theperimeter of the gate electrode 116, while in other embodiments theoxide layer 114 may cover and/or be formed over the entirety of the wellregion 101.

According to various embodiments, the transistor 104 includes a gateelectrode 116 on the oxide layer 114. The gate electrode 116 may beimplemented as a stack structure formed on the oxide layer 114. Invarious embodiments where the gate electrode 116 is implemented as astack structure, the gate electrode 116 may include a semiconductorlayer, such as an n-type or p-type polysilicon, formed on the oxidelayer 114. In at least one embodiment the semiconductor layer isimplemented as a combination of several p-type and n-type polysiliconstructures. According to various embodiments, the gate electrode mayhave a conductive layer 116 a formed over the semiconductor layer. In atleast one embodiment, this conductive layer may be a self-alignedsilicide layer, e.g. a cobalt silicide, titanium silicide, nickelsilicide, platinum silicide, and/or a tungsten silicide. In someembodiments, the conductive layer 116 a may be formed of a metallicmaterial, a metalized material, a metal foil, an elemental metal, and/ora metal alloy. The conductive layer 116 a may have a thickness betweenabout 2 nm and about 15 nm. According to various embodiments, conductivelayer 116 a may have any thickness that may be desirable for a givenapplication. In various embodiments, the transistor 104 might include atleast one spacer structure 116 c on at least one sidewall of the stackstructure. The spacer structure 116 c may be implemented as variousnitrides, in some embodiments; the spacer structure 116 c may include oressentially consist of tetraethyl orthosilicate. According to variousembodiments, the transistor structure 100 includes an electrical contact116 b formed and/or arranged over a top side of the gate electrode 130.In some embodiments, the electrical contact 116 b may be formed of ametallic material, a metalized material, a metal foil, an elementalmetal, and/or a metal alloy. The electrical contact 116 b may include ormay essentially consist of cobalt silicide, titanium silicide, nickelsilicide, platinum silicide, and/or a tungsten silicide.

According to various embodiments, the transistor structure 100 includesa source electrode 118 formed over and/or on a surface of the firstdiffusion region 104 a. In some embodiments, the source electrode 118 iselectrically coupled and/or in electrical contact or communication withthe first diffusion region 104 a. In some embodiments, the sourceelectrode 118 includes a base layer 118 a formed on a surface of thefirst diffusion region 104 a and a conductive extension 118 b formed onthe base layer 118 a. The base layer 118 a may be a self-alignedsilicide layer, e.g. a cobalt silicide, titanium silicide, nickelsilicide, platinum silicide, and/or a tungsten silicide. In someembodiments, the base layer 118 a may be formed of a metallic material,a metalized material, a metal foil, an elemental metal, and/or a metalalloy. In some embodiments, the conductive extension 118 b may be formedof a metallic material, a metalized material, an elemental metal, and/ora metal alloy. In at least one embodiment, the base layer 118 a and theconductive extension 118 b may be formed together, i.e. may consist of amonolithic structure, while in other embodiments the base layer 118 aand the conductive extension 118 b are formed in discrete steps.

According to various embodiments, the transistor structure 100 includesa drain electrode 120 formed over and/or on a surface of the seconddiffusion region 104 b. In some embodiments, the drain electrode 120 iselectrically coupled and/or in electrical contact or communication withthe second diffusion region 104 b. In some embodiments, the drainelectrode 120 incudes a base layer 120 a formed on a surface of thesecond diffusion region 104 b and a conductive extension 120 b formed onthe base layer 120 a. The base layer 120 a may be substantially similarto the base layer 118 a, and the conductive extension 120 b may besubstantially similar to the conductive extension 118 b, describedabove.

According to various embodiments, the transistor structure 100 includesat least one body connection electrode 122 formed on the structure ofthe first impurity type 110. In some embodiments, the at least one bodyconnection electrode 122 is electrically coupled and/or in electricalcontact or communication with the structure of the first impurity type110. In some embodiments, the at least one body connection electrode 122is electrically coupled and/or in electrical contact or communicationwith the first diffusion region 104 a, while in other embodiments the atleast one body connection is electrically coupled to the seconddiffusion region 104 b. In some embodiments, the at least one bodyconnection electrode 122 incudes a base layer 122 a formed on a surfaceof the structure of the first impurity type 110 and a conductiveextension 122 b formed on the base layer 122 a. The base layer 122 a maybe substantially similar to the base layer 118 a, and the conductiveextension 122 b may be substantially similar to the conductive extension118 b, described above.

According to various embodiments, the transistor structure 100 includesat least one lightly doped source region 124 extending from theperimeter of the first diffusion region 104 a and into the channel 108.In some embodiments, the lightly doped source region 124 is implementedas a p-type impurity doped region in the well region 101. In someembodiments, the lightly doped source region 124 is implemented as ann-type impurity doped region in the well region 101. In someembodiments, the lightly doped source region may have an impurityconcentration from about b 10 ¹⁶ cm⁻³ to about 10¹⁹ cm⁻³. The lightlydoped source region 124 may be formed in the substrate 102 and/or wellregion 101 through various techniques, e.g. vapor-phase epitaxy,diffusion, and/or ion implantation, etc.

According to various embodiments, the transistor structure 100 includesat least one lightly doped drain region 126 of the second impurity typeextending from the perimeter of the second diffusion region 106 and intothe channel 108. In some embodiments, the lightly doped drain region 126is implemented as a p-type impurity doped region in the well region 101.In some embodiments, the lightly doped drain region 126 is implementedas an n-type impurity doped region in the well region 101. In someembodiments, the lightly doped drain region may have an impurityconcentration from about 10¹⁶ cm⁻³ to about 10¹⁹ cm⁻³. The lightly dopeddrain region 126 may be formed in the substrate 102 and/or well region101 through various techniques, e.g. vapor-phase epitaxy, diffusion,and/or ion implantation, etc. In various embodiments, the transistorstructure 100 includes at least one defined border 128 where the oxidelayer 114 stops and the trench or field oxide isolation layer 112begins. In other words the border 128 is a well-defined transitionregion between the oxide layer 114 and the trench or field oxideisolation layer 112, i.e. a border where the oxide layer 114 and thetrench or field oxide isolation layer 112 are in physical contact.

According to various embodiments, as illustrated in FIG. 4, thetransistor structure 100 can be implemented as a type ofmulti-transistor structure 400. In various embodiments, themulti-transistor structure 400 includes a well region 401. The wellregion 401 may be substantially similar to the well region 101,described above, and may be formed through many of the processes and maycontain many of the same physical and/or electrical properties. Invarious embodiments, the multi-transistor structure 400 includessubstrate 402. The substrate 402 may be substantially similar to thesubstrate 102, described above, and may be formed through many of theprocesses and may contain many of the same properties. Themulti-transistor structure 400 is similar to the transistor structure100 in many respects, differing mainly in the number of transistors 404it contains. The illustrative embodiment of the multi-transistorstructure 400, depicted in FIG. 4 contains four transistors, representedby reference FIGS. 404a-404d . The transistors 404 a-404 d may besubstantially similar to the at least one transistor 104 and may beformed through many of the processes described above. According tovarious embodiments, the transistors 404 a-404 d are each implementedwith independent source diffusion regions 406 a-406 d. The sourcediffusion regions 406 a-406 d are analogous to the first and seconddiffusion regions 104 a and 104 b, respectively, described above and maybe formed using many of the same processes. According to variousembodiments, the transistors 404 a-404 d are each implemented withsource electrodes 408 a-408 d. The source electrodes 408 a-408 d areanalogous to the source electrode 118 described above and may beimplemented using many of the same materials and processes. According toan embodiment, the multi-transistor structure 400 contains a commondrain diffusion region 410. The common drain diffusion region 410 may belocated in a central portion of the multi-transistor structure 400. Insome embodiments, the common drain diffusion region 410 is arrangedbetween the source electrodes 408 a-408 d. In the embodiment depicted inFIG. 4, the source electrodes 408 a-408 d are arranged around theperimeter of the common drain diffusion region 410 in a cross-likeconfiguration, however it should be noted that this geometry isexemplary and not intended to be limiting. The source electrodes 408a-408 d may be arranged around the common drain diffusion region 410 ina variety of configurations, e.g. in some embodiments the common draindiffusion region 410 and the source electrodes 408 a-408 d may beparallel to each other. According to an embodiment, the common draindiffusion region 410 is analogous to the first and second diffusionregions 104 a and 104 b, respectively, described above and may be formedusing many of the same processes and materials. According to anembodiment, the multi-transistor structure 400 contains a common drainelectrode 412. The common drain electrode 412 is analogous to the drainelectrode 120 described above and may be implemented using many of thesame materials and processes. According to an embodiment, the commondrain electrode 412 and the common drain diffusion region 410 arecoextensive and/or substantially overlap one another. According to anembodiment, the multi-transistor structure 400 contains a channel regionfor each of the transistors it may contain. In the embodiment depictedin FIG. 4, the multi-transistor structure 400 is implemented with fourchannel regions 414 a-414 d for each of the transistors 404 a-404 d.According to various embodiments, the channel regions 414 a-414 d areanalogous to the channel 108 described above and may be implementedusing many of the same materials and processes. In various embodiments,the length and width of each of the channel regions 414 a-414 d aredepicted by references figures W_(x) and L_(x) in FIG. 4, i.e. channelregion 414 a has a width W₁ and a length L₁, etc. According to anembodiment, the multi-transistor structure 400 contains a gate oxidelayer 416. In various embodiments, the gate oxide layer 416 is formedover the common drain diffusion region 410 and extends over each of thechannel regions 414 a-414 d, with a defined border interface 420 wherethe gate oxide layer 416 switches to the trench or field oxide layer422. According to various embodiments, the gate oxide layer 416 isanalogous to the oxide layer 114 described above and may be implementedusing many of the same materials and processes. According to anembodiment, the multi-transistor structure 400 contains a gate electrodestructure 418, which may be implemented as a gate base layer 418 a and aplurality of gate contacts 418 b. In the embodiment depicted in FIG. 4,the gate base layer 418 a is shown in transparency for clarity of detailof the other elements contained in the multi-transistor structure 400.The gate electrode structure 418 is analogous to gate electrode 116 andmay be formed using many of the same processes and material and mayshare many of the same physical and/or electrical properties as the gateelectrode 116. According to an embodiment, the multi-transistorstructure 400 contains a border interface 420 where the field oxide orshallow trench isolation layer 422 is located outside of the gate oxidelayer 416. The shallow trench or field oxide isolation layer 422 isanalogous to the trench or field oxide isolation layer 112 and may beformed from the same and/or similar materials and may share many of thesame physical and/or electrical properties as the trench or field oxideisolation layer 112. According to an embodiment, the multi-transistorstructure 400 contains a bulk diffusion region 424 in the substrate 402enclosing the well region 401. According to various embodiments, thebulk diffusion region 424 is implemented as a bulk diffusion region forconnection to the well region 401. The bulk diffusion region 424 isanalogous to the structure of the first impurity type 110 and may beformed from the same and/or similar materials and may share many of thesame physical and/or electrical properties as the structure of the firstimpurity type 110. According to various embodiments, themulti-transistor structure 400 contains at least one body connectionelectrode 430 formed on the bulk diffusion region 424. In someembodiments, the at least one body connection electrode 430 is analogousto the at least one body connection electrode 122, described in detailabove, and may be formed from the same and/or similar materials and mayshare many of the same physical and/or electrical properties as the atleast one body connection electrode 122. In some embodiments, the atleast one body connection electrode 430 incudes a base layer 430 aformed on a surface of the bulk diffusion region 424 and a conductiveextension 430 b formed on the base layer 430 a. According to variousembodiments, the base layer 430 a is analogous to the base layer 122 a,described in detail above, and may be formed from the same and/orsimilar materials and may share many of the same physical and/orelectrical properties. Similarly, conductive extension 430 b isanalogous to the conductive extension 122 b, described in detail above,and may be formed from the same and/or similar materials and may sharemany of the same physical and/or electrical properties.

According to various embodiments, as illustrated in FIG. 5, thetransistor structure 100 can be implemented as a type ofmulti-transistor structure 500. In various embodiments, themulti-transistor structure 500 includes a well region 501. The wellregion 501 may be substantially similar to the well region 101,described above, and may be formed through many of the processes and maycontain many of the same physical and/or electrical properties. Invarious embodiments, the multi-transistor structure 500 includes asubstrate 502. The substrate 502 may be substantially similar to thesubstrate 102, described above, and may be formed through many of theprocesses and may contain many of the same properties. Themulti-transistor structure 500 may be similar or identical to thetransistor structure 100 in many respects, differing mainly in thenumber of transistors 504 it contains. The illustrative embodiment ofthe multi-transistor structure 500, depicted in FIG. 5 contains eighttransistors, represented by reference FIGS. 504a -504 h. The transistors504 a-504 h may be substantially similar to the at least one transistor104 and may be formed through many of the processes described above.According to various embodiments, the transistors 504 a-504 h are eachimplemented with independent source diffusion regions 506 a-506 h. Thesource diffusion regions 506 a-506 h are analogous to the firstdiffusion region 104 a, described above and may be formed using many ofthe same processes. According to various embodiments, the transistors504 a-504 h are each implemented with source electrodes 508 a-508 h. Thesource electrodes 408 a-408 d are analogous to the source electrode 118described above and may be implemented using many of the same materialsand processes. According to an embodiment, the multi-transistorstructure 500 contains a common drain diffusion region 510. The commondrain diffusion region 510 may be located in a central portion of themulti-transistor structure 500. In some embodiments, the common draindiffusion region 510 is arranged between the source electrodes 508 a-508h. In the embodiment depicted in FIG. 5, the source electrodes 508 a-508h are arranged around the perimeter of the common drain diffusion region510 in an octagonal configuration, however it should be noted that thisgeometry is exemplary and not intended to be limiting. The sourceelectrodes 508 a-508 h may be arranged around the common drain diffusionregion 510 in a variety of configurations, e.g. in some embodiments thecommon drain diffusion region 510 and the source electrodes 508 a-508 hmay be parallel to each other. According to an embodiment, the commondrain diffusion region 510 is analogous to the second diffusion region104 b, described above and may be formed using many of the sameprocesses and materials. According to an embodiment, themulti-transistor structure 500 contains a common drain electrode 512.The common drain electrode 512 is analogous to the drain electrode 120described above and may be implemented using many of the same materialsand processes. According to an embodiment, the common drain electrode512 and the common drain diffusion region 510 are coextensive and/orsubstantially overlap one another. According to an embodiment, themulti-transistor structure 500 contains a channel region for each of thetransistors it may contain. In the embodiment depicted in FIG. 5, themulti-transistor structure 500 is implemented with eight channel regions514 a-514 h for each of the transistors 504 a-504 h. According tovarious embodiments, the channel regions 514 a-514 h are analogous tothe channel 108 described above and may be implemented using many of thesame materials and processes. In various embodiments, the length andwidth of each of the channel regions 514 a-514 h are depicted byreferences figures W_(x) and L_(x) in FIG. 5, i.e. channel region 514 ahas a width W₁ and a length L₁, etc. According to an embodiment, themulti-transistor structure 500 contains an oxide layer 516. In variousembodiments, the oxide layer 516 is formed over the common draindiffusion region 510 and extends over each of the channel regions 514a-514 h. According to various embodiments, the oxide layer 516 isanalogous to the oxide layer 114 described above and may be implementedusing many of the same materials and processes. According to anembodiment, the multi-transistor structure 500 contains a gate electrodestructure 518, which may be implemented as a gate base layer 518 a and aplurality of gate contacts 518 b. In the embodiment depicted in FIG. 5,the gate base layer 518 a is shown in transparency for clarity of detailof the other elements contained in the multi-transistor structure 500.The gate electrode structure 518 is analogous to gate electrode 116 andmay be formed using many of the same processes and material and mayshare many of the same physical and/or electrical properties as the gateelectrode 116. According to an embodiment, the multi-transistorstructure 500 contains a boarder interface 520 with the gate oxide layer516 inside a shallow trench or field oxide isolation layer 522 outsidethe transistor channel regions 514 a-514 h. In various embodiments, theborder interface 520 is a region where the gate oxide layer 516 stopsand the trench or field oxide isolation layer 522 begins. In other wordsthe border interface 520 is a well-defined transition region between thegate oxide layer 516 and the trench or field oxide isolation layer 522,i.e. a border where the gate oxide layer 516 and the trench or fieldoxide isolation layer 522 are in physical contact. The shallow trenchisolation layer 522 is analogous to the trench or field oxide isolationlayer 112 and may be formed from the same and/or similar materials asthe trench or field oxide isolation layer 112. Further, in anembodiment, the shallow trench isolation layer 522 serves the samepurpose the trench or field oxide isolation layer 112. According to anembodiment, the multi-transistor structure 500 contains a bulk diffusionregion 524 in the substrate 502 enclosing the well region 501. Accordingto various embodiments, the bulk diffusion region 524 is implemented asa bulk diffusion region for connection to the well region 501. The bulkdiffusion region 524 is analogous to the structure of the first impuritytype 110 and may be formed from the same and/or similar materials andmay share many of the same physical and/or electrical properties as thestructure of the first impurity type 110. According to variousembodiments, the multi-transistor structure 500 contains at least onebody connection electrode 530 formed on the bulk diffusion region 524.In some embodiments, the at least one body connection electrode 530 isanalogous to the at least one body connection electrode 122, describedin detail above, and may be formed from the same and/or similarmaterials and may share many of the same physical and/or electricalproperties as the at least one body connection electrode 122. In someembodiments, the at least one body connection electrode 530 incudes abase layer 530 a formed on a surface of the bulk diffusion region 524and a conductive extension 530 b formed on the base layer 530 a.According to various embodiments, the base layer 530 a is analogous tothe base layer 122 a, described in detail above, and may be formed fromthe same and/or similar materials and may share many of the samephysical and/or electrical properties. Similarly, conductive extension530 b is analogous to the conductive extension 122 b, described indetail above, and may be formed from the same and/or similar materialsand may share many of the same physical and/or electrical properties.

According to various embodiments, as illustrated in FIG. 6, thetransistor structure 100 can be implemented as a type ofmulti-transistor structure 600. In various embodiments, themulti-transistor structure 600 includes a well region 601. The wellregion 601 may be substantially similar to the well region 101,described above, and may be formed through many of the processes and maycontain many of the same physical and/or electrical properties. Invarious embodiments, the multi-transistor structure 600 includessubstrate 602. The substrate 602 may be substantially similar to thesubstrate 102, described above, and may be formed through many of theprocesses and may contain many of the same properties. Themulti-transistor structure 600 may be similar or identical to thetransistor structure 100 in many respects, differing mainly in thenumber of transistors 604 it contains. The illustrative embodiment ofthe multi-transistor structure 600, depicted in FIG. 6 contains acontinuous and/or infinitely divisible transistor 604. The continuoustransistor 604 depicted in FIG. 6 may be substantially similar to the atleast one transistor 104 and may be formed through many of the processesdescribed above. According to various embodiments, the continuoustransistor 604 is implemented with a source diffusion region 606. Thesource diffusion region 606 is analogous to the first diffusion region104 a, described above, and may be formed using many of the sameprocesses. In the embodiment depicted in FIG. 6, the source diffusionregion 606 is implemented as an annular diffusion region, however itshould be noted that this geometry is exemplary and not intended to belimiting. According to various embodiments, the continuous transistor isimplemented with a continuous source electrode 608. The continuoussource electrode 608 is analogous to the source electrode 118 describedabove and may be implemented using many of the same materials andprocesses. In the embodiment depicted in FIG. 6, the continuous sourceelectrode 608 is impended as an annular structure, however it should benoted that this geometry is exemplary and not intended to be limiting.According to an embodiment, the continuous source electrode 608 and thesource diffusion region 606 are coextensive and/or substantially overlapone another, in other words the continuous source electrode 608 isformed over and/or directly on the source diffusion region 606.According to an embodiment, the multi-transistor structure 600 containsa common drain diffusion region 610. The common drain diffusion region610 may be located in a central portion of the multi-transistorstructure 600. In some embodiments, the common drain diffusion region610 is arranged between inside the annular continuous source electrode608. In the embodiment depicted in FIG. 6, the continuous sourceelectrode 608 and the common drain diffusion region 610 are depicted asconcentric annular structures, however it should be noted that thisgeometry is exemplary and not intended to be limiting. According to anembodiment, the common drain diffusion region 610 is analogous to thesecond diffusion region 104 b, described above, and may be formed usingmany of the same processes and materials. According to an embodiment,the multi-transistor structure 600 contains a common drain electrode612. The common drain electrode 612 is analogous to the drain electrode120 described above and may be implemented using many of the samematerials and processes. According to an embodiment, the common drainelectrode 612 and the common drain diffusion region 610 are coextensiveand/or substantially overlap one another. According to an embodiment,the multi-transistor structure 600 contains a portion of the well region601 implemented as a transistor channel region 614, in FIG. 6 thechannel region 614 is obscured by the gate base layer 618 a. In variousembodiments, the length and width of each of the transistor channelregion 614 is depicted by references figures W and L in FIG. 6.According to an embodiment, the multi-transistor structure 600 containsan oxide layer 616 disposed over the channel region 614. The oxide layer616 is analogous to the oxide layer 114, described above, and may beformed from the same and/or similar materials. According to anembodiment, the multi-transistor structure 600 contains a gate electrodestructure 618, which may be implemented as a gate base layer 618 a and aplurality of gate contacts 618 b. The gate electrode structure 618 isanalogous to gate electrode 116 and may be formed using many of the sameprocesses and material and may share many of the same physical and/orelectrical properties as the gate electrode 116. According to anembodiment, the multi-transistor structure 600 contains a borderinterface 620 to separate the gate oxide layer 616 from the shallowtrench or field oxide isolation layer 622. In other words the borderinterface 620 is a well-defined transition region between the oxidelayer 616 and the trench or field oxide isolation layer 622, i.e. aborder where the oxide layer 616 and the trench or field oxide isolationlayer 622 are in physical contact. The shallow trench isolation layer622 is analogous to the trench or field oxide isolation layer 112 andmay be formed from the same and/or similar materials as the trench orfield oxide isolation layer 112. According to an embodiment, themulti-transistor structure 600 contains a bulk diffusion region 624 inthe substrate 602 enclosing the well region 601. According to variousembodiments, the bulk diffusion region 624 is implemented as a bulkdiffusion region for connection to the well region 601. The bulkdiffusion region 624 is analogous to the structure of the first impuritytype 110 and may be formed from the same and/or similar materials andmay share many of the same physical and/or electrical properties as thestructure of the first impurity type 110. According to variousembodiments, the multi-transistor structure 600 contains at least onebody connection electrode 630 formed on the bulk diffusion region 624.In some embodiments, the at least one body connection electrode 630 isanalogous to the at least one body connection electrode 122, describedin detail above, and may be formed from the same and/or similarmaterials and may share many of the same physical and/or electricalproperties as the at least one body connection electrode 122. In someembodiments, the at least one body connection electrode 630 includes abase layer 630 a formed on a surface of the bulk diffusion region 624and a conductive extension 630 b formed on the base layer 630 a.According to various embodiments, the base layer 630 a is analogous tothe base layer 122 a, described in detail above, and may be formed fromthe same and/or similar materials and may share many of the samephysical and/or electrical properties. Similarly, conductive extension630 b is analogous to the conductive extension 122 b, described indetail above, and may be formed from the same and/or similar materialsand may share many of the same physical and/or electrical properties.

The following examples pertain to further embodiments.

In Example 1, a transistor structure, which includes a substrate; a wellregion of a first impurity type in the substrate; at least onetransistor formed at least partially on the well region, a portion ofthe well region comprising a transistor channel; a structure of thefirst impurity type in the substrate enclosing the well region; and atrench and/or field oxide isolation layer in the substrate enclosing thestructure; where a concentration of the first impurity type in thestructure enclosing the well region is higher than a concentration ofthe first impurity type in the well region.

In Example 2, the transistor structure of Example 1, where the firstimpurity type is a p-type dopant and the second impurity type is ann-type dopant.

In Example 3, a transistor structure, which includes a substrate; a wellregion of a first impurity type in the substrate; at least onetransistor formed at least partially on the well region, the transistorhaving a drain region in the well region and a plurality of sourceregions at least partially in the well region, said source regions beingarranged around the gate region; the well region including a pluralityof channels separating the drain region from the plurality of sourceregions; a structure of the first impurity type in the substrateenclosing the well region; and a trench and/or field oxide isolationlayer in the substrate enclosing the isolation structure; where aconcentration of the first impurity type in the structure enclosing thewell region is higher than a concentration of the first impurity type inthe well region.

In Example 4, the transistor structure of Example 3, further includes anoxide layer over the well region which surrounds the drain region andextends over each of the channels from the plurality and/or overlaps thechannel-regions, known from classical CMOS-transistor layouts, definedby W (channel-width); and a gate electrode on the oxide layer, e.g. thechannel-width is not determined any more by the lateral interface of theoxide-layer (GOX) and the field-oxide layer (e.g. LOCOS or STI), as itis state of the art today in a classical CMOS-transistor.

The definition of the channel length remains un-changed, as known fromstat of the art, determined by the length of the gate-electrode betweensource and drain.

In Example 5, the transistor structure of Example 3 & 4, where a lateralextension of the oxide layer is bounded by the structure of the firstimpurity type.

In Example 6, the transistor structure Examples 3-5, where the drainregion includes a substantially square structure; and the plurality ofsource regions include four source regions arranged around the perimeterof the drain region in a substantially cross-shaped configuration.

In Example 7, the transistor structure of Examples 3-5, where the drainregion includes a substantially octagonal structure; and the pluralityof source regions include eight source regions arranged around theperimeter of the drain diffusion region in a substantially octagonalconfiguration. Generally the drain region is determined by a2^(n)-corner structure and 2 ^(n) sources are arranged around the commondrain diffusion.

n=1,2,3,4 . . . ∞

In Example 8, the transistor structure of Examples 3-5, where the drainregion includes a substantially circular structure; and the plurality ofsource regions includes a substantially annular structure concentricallyarranged with the drain region. Compare to Example 7: n=∞.

In Example 9, the transistor structure of Example 8, where the gateelectrode includes a substantially annular structure situatedconcentrically with the drain region and a planar section extending overthe drain region and the plurality of source regions.

In Example 10, the at least one field effect transistor of Examples 3-9,where the first impurity type is a p-type dopant and the second impuritytype is an n-type dopant; or or: where the first impurity type is an-type dopant and a second impurity type is an p-type dopant.

In Example 11, at least one field effect transistor includes asubstrate; a gate dielectric layer on the substrate; and a trench or afield oxide isolation layer in the substrate enclosing the gatedielectric layer; where the gate dielectric layer is structured suchthat it does not extend over the trench isolation layer.

In Example 12, the at least one field effect transistor of Example 11further includes a well region of a first impurity type in thesubstrate; and at least one transistor gate formed at least partially onthe well region, a portion of the well region including a least onetransistor channel; where the gate dielectric layer is arranged betweenthe at least one transistor gate and the at least one transistorchannel.

In Example 13, the at least one field effect transistor of Examples 11 &12 further includes a ring structure of the first impurity type arrangedin the substrate between the well region and the trench and/or fieldoxide isolation layer; where a concentration of the first impurity typein the ring structure is higher than a concentration of the firstimpurity type in the well region.

In Example 14, the at least one field effect transistor of Example 13,where a lateral extension of the gate dielectric layer is bounded and/orterminated by a ring structure for source or drain diffusion.

In Example 15, the at least one field effect transistor of Examples11-14 further includes a drain region in the well region and a pluralityof source regions at least partially in the well region, said sourceregions being arranged around the at least one transistor gate.

In Example 16, the at least one field effect transistor of Example 15,where the plurality of source regions include four source regionsarranged around the perimeter of the drain region in a substantiallycross-shaped configuration; and where the well region includes fourtransistor channels, one channel formed between each source region and acorresponding portion of the drain region.

In Example 17, the at least one field effect transistor of Example 15,where the plurality of source regions includes eight source regionsarranged around the perimeter of the drain diffusion region in asubstantially octagonal configuration; and where the well regionincludes eight transistor channels, one channel formed between eachsource region and a corresponding portion of the drain region. Generallythe number of transistor-channels is determined by 2n, n=1,2,3,4 . . . ∞

In Example 18, the at least one field effect transistor of Example 15,where the drain region includes a substantially circular structure; andthe plurality of source regions includes a substantially annularstructure concentrically arranged with the drain region. See Example 17:n=∞.

In Example 19, the at least one field effect transistor of Example 18,where the gate electrode includes an annular structure situatedconcentrically with the drain region and a planar section extending fromthe annular structure over the drain region and the plurality of sourceregions. Optional the source region might be placed in the center ascommon source diffusion surrounded by a plurality of drain regions.

In Example 20, the at least one field effect transistor of Examples11-19, where the first impurity type is a p-type dopant and the secondimpurity type is an n-type dopant; or: where the first impurity type isa n-type dopant and a second impurity type is a p-type dopant.

In Example 21, a transistor structure which includes a substrate; a wellregion of a first impurity type in the substrate; a first diffusionregion of a second impurity type in the well region; a second diffusionregion of the second impurity type in the well region, a portion of thewell region forming a channel separating the first diffusion region andthe second diffusion region; an isolation structure of the firstimpurity type in the substrate enclosing the well region; and a trenchisolation layer in the substrate enclosing the isolation structure;where a concentration of the first impurity type in the isolationstructure is higher than a concentration of the first impurity type inthe well region.

In Example 22, the transistor structure of Example 21 further includesan oxide layer over the channel; a gate electrode on the oxide layer; asource electrode on the first diffusion region; a drain electrode on thesecond diffusion region; and at least one body connection electrode onthe isolation structure.

In Example 23, the transistor structure of Examples 21 and 22 furtherincludes at least one lightly doped drain region of the second impuritytype extending from the perimeter of the first diffusion region and intothe channel, the at least one lightly doped drain region having aconcentration of the second impurity type which is lower than aconcentration of the second impurity type in the first diffusion region;and at least one lightly doped drain region of the second impurity typeextending from the perimeter of the second diffusion region and into thechannel, the at least one lightly doped drain region having aconcentration of the second impurity type which is lower than aconcentration of the second impurity type in the second diffusionregion.

In Example 24, the transistor structure of Examples 21 & 23, where thegate electrode includes a stack layer formed on the oxide layer and aspacer structure on at least one sidewall of the stack layer.

In Example 25, the transistor structure of Examples 21-24, where thesource electrode is electrically coupled to the at least one bodyconnection electrode.

In Example 26, the transistor structure of Examples 21-25, where thefirst impurity type includes a p-type dopant and the second impuritytype includes an n-type dopant.

In Example 27, a transistor structure, which includes a substrate; awell region of a first impurity type in the substrate; a primarydiffusion region of a second impurity type in the well region; aplurality of secondary diffusion regions of the second impurity type inthe well region arranged around the perimeter of the primary diffusionregion; the well region including a plurality of channels separating theprimary diffusion region from the secondary diffusion regions; anisolation structure of the first impurity type in the substrateenclosing the well region; and a trench isolation layer in the substrateenclosing the isolation structure; where a concentration of the firstimpurity type in the isolation structure is higher than a concentrationof the first impurity type in the well region.

In Example 28, the transistor structure of Example 27, further includingan oxide layer over the well region which surrounds the primarydiffusion region and extends over each of the channels from theplurality; a gate electrode on the oxide layer; at least one drainelectrode in the primary diffusion region; at least one source electrodein each of the secondary diffusion regions; and at least one bodyconnection electrode in the isolation structure.

In Example 29, the transistor structure of Examples 27 & 28, where gateelectrode includes a stack layer formed on the oxide layer and a atleast one gate contact formed on the gate electrode.

In Example 30, the transistor structure of Examples 27-29, where atleast one source electrode from each of the secondary diffusion regionsis electrically coupled to the at least one body connection electrode.

In Example 31, the transistor structure of Examples 27-30, where theprimary diffusion region is a transistor drain region; and the pluralityof secondary diffusion regions is a plurality of transistor sourceregions.

In Example 32, the transistor structure of Examples 27-31, where theplurality of secondary diffusion regions includes four diffusion regionsarranged around the perimeter of the primary diffusion region to form asubstantially cross-shaped configuration.

In Example 33, the transistor structure of Examples 27-32, where theplurality of secondary diffusion regions includes eight diffusionregions arranged around the perimeter of the primary diffusion region ina substantially octagonal configuration.

In Example 34, the transistor structure of Examples 27-33, where theprimary diffusion region includes a substantially circular structureand; where the plurality of secondary diffusion regions includessubstantially annular structure concentrically arranged with the primarydiffusion region.

In Example 35, the transistor structure of Examples 27-34, where and thegate electrode includes a substantially annular structure situatedconcentrically with the primary diffusion region and a planar sectionextending over the primary diffusion region and the secondary diffusionregion.

In Example 36, a method of forming a transistor structure, the methodincluding providing a substrate; forming a well region of a firstimpurity type in the substrate; forming a first diffusion region of asecond impurity type in the well region; forming a second diffusionregion of the second impurity type in the well region, shaping a portionof the well region to form a channel separating the first diffusionregion and the second diffusion region; forming an isolation structureof the first impurity type in the substrate to enclose the well region;and forming a trench isolation layer in the substrate to enclose theisolation structure; where a concentration of the first impurity type inthe isolation structure is higher than a concentration of the firstimpurity type in the well region.

In Example 37, the method of Example 36 further includes forming anoxide layer over the channel; providing a gate electrode on the oxidelayer; forming a source electrode on the first diffusion region; forminga drain electrode on the second diffusion region; and forming at leastone body connection electrode on the isolation structure.

In Example 38, the method of Examples 36 & 37 further includes formingat least one lightly doped drain region of the second impurity typeextending from the perimeter of the first diffusion region and into thechannel, the at least one lightly doped drain region having aconcentration of the second impurity type which is lower than aconcentration of the second impurity type in the first diffusion region;and forming at least one lightly doped drain region of the secondimpurity type extending from the perimeter of the second diffusionregion and into the channel, the at least one lightly doped drain regionhaving a concentration of the second impurity type which is lower than aconcentration of the second impurity type in the second diffusionregion.

In Example 39, a method for forming a transistor structure includesproviding a substrate; forming a well region of a first impurity type inthe substrate; forming a primary diffusion region of a second impuritytype in the well region; forming a plurality of secondary diffusionregions of the second impurity type in the well region; arranging theplurality of secondary diffusion regions around the perimeter of theprimary diffusion region; forming the well region into a plurality ofchannels separating the primary diffusion region from the secondarydiffusion regions; forming an isolation structure of the first impuritytype in the substrate enclosing the well region; and providing a trenchisolation layer in the substrate enclosing the isolation structure;where a concentration of the first impurity type in the isolationstructure is higher than a concentration of the first impurity type inthe well region.

In Example 40, the method of Example 39 further includes forming anoxide layer over the well region and shaping the oxide layer to surroundthe primary diffusion region and extend over each of the channels fromthe plurality; providing a gate electrode on the oxide layer; forming atleast one drain electrode in the primary diffusion region; forming atleast one source electrode in each of the secondary diffusion regions;and forming at least one body connection electrode in the isolationstructure.

What is claimed is:
 1. At least one field effect transistor comprising:a substrate; a gate dielectric layer on the substrate; and an isolationlayer in the substrate surrounding the gate dielectric layer.
 2. The atleast one field effect transistor of claim 1, further comprising: a wellregion of a first impurity type in the substrate; and at least onetransistor gate formed at least partially on the well region, a portionof the well region comprising a least one transistor channel; whereinthe gate dielectric layer is arranged between the at least onetransistor gate and the at least one transistor channel.
 3. The at leastone field effect transistor of claim 2, further comprising: a ringstructure of the first impurity type arranged in the substrate betweenthe well region and the isolation layer; wherein a concentration of thefirst impurity type in the ring structure is higher than a concentrationof the first impurity type in the well region.
 4. The at least one fieldeffect transistor of claim 3, wherein a lateral extension of the gatedielectric layer is bounded by the ring structure.
 5. The at least onefield effect transistor of claim 2, further comprising: a drain regionin the well region and a plurality of source regions at least partiallyin the well region, said source regions being arranged around the atleast one transistor gate.
 6. The at least one field effect transistorof claim 5, wherein the plurality of source regions comprise four sourceregions arranged around the perimeter of the drain region in asubstantially cross-shaped configuration; and wherein the well regioncomprises four transistor channels, one channel formed between eachsource region and a corresponding portion of the drain region.
 7. The atleast one field effect transistor of claim 5, wherein the plurality ofsource regions comprise eight source regions arranged around theperimeter of the drain diffusion region in a substantially octagonalconfiguration; and wherein the well region comprises eight transistorchannels, one channel formed between each source region and acorresponding portion of the drain region.
 8. The at least one fieldeffect transistor of claim 5, wherein the drain region comprises asubstantially circular structure; and wherein the plurality of sourceregions comprise a substantially annular structure concentricallyarranged with the drain region.
 9. The at least one field effecttransistor of claim 8, wherein the gate electrode comprises an annularstructure situated concentrically with the drain region and a planarsection extending from the annular structure over the drain region andthe plurality of source regions.
 10. The at least one field effecttransistor of claim 1, wherein the first impurity type comprises ap-type dopant and a second impurity type comprises an n-type dopant; orwherein the first impurity type comprises a n-type dopant and a secondimpurity type comprises an p-type dopant.